1. Technical Field
The invention relates generally to semiconductor device fabrication, and more particularly, to methods of forming and a resulting dual metal gate using one metal to alter a work function of another metal.
2. Background Art
Recently, there has been substantial interest in replacing polysilicon gate conductors with metal gate electrodes, so that the gate conductor is a metal in both n-type and p-type metal oxide semiconductor (NMOS and PMOS) devices. In order to provide appropriate threshold voltages in the two types of devices, two different metals are typically needed. In addition, the NMOS and PMOS devices require metals with different work functions. The “work function” of a material is a measurement of how much energy is required to extract an electron from the material by moving the electron in the solid from the Fermi level to the vacuum level, i.e., to outside of the solid.
Conventionally, the two metals used are selected based on their work function and ease of integration in terms of wet and dry etching depending on the method of implementation. There are several different integration schemes used to realize two different metal layers on the same wafer to form dual metal gates. Referring to FIGS. 1A-1E, one of the most simple and well accepted schemes is illustrated. As shown, in a first step, a first metal layer 10 is deposited over a gate dielectric layer 12. Both layers 10, 12 are over a substrate 14 having an NMOS region 20 separated from a PMOS region 22 by a trench isolation 24. First metal layer 10 can be an NMOS metal or a PMOS metal, primarily depending on the ease of removal possible without damaging an underlying gate dielectric layer 12. Usually the NMOS metal (e.g., tantalum silicon nitride (TaSiN), titanium nitride (TiN), tantalum nitride (TaN)) has a work function close to the silicon conduction band and exhibits a tendency towards dissolution in common wet chemistries such as a sulfuric peroxide mixture (SPM), SC1 (NH4OH:H2O2:H2O mixture) or hydrogen peroxide (H2O2). On the other hand, PMOS metals (e.g., ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt)) have work functions close to the silicon valence band and are more inert and difficult to etch in wet chemistries that are typically used in normal microelectronic fabrication. Due to the ease of wet etching, the NMOS metal is usually used as first metal layer 10. The following description is based on that assumption.
Next, as shown in FIGS. 1A-1D, first metal 10 is selectively etched away over a region 20 or 22 (PMOS region 22 as shown) to gate dielectric layer 12. Since the metal removal process attacks typical photo resist materials, a lithography process is used to open PMOS region 20 using (hard) masking material 30 such as an amorphous silicon layer. In particular, a masking material 30 is deposited and a photoresist 32 is patterned and etched, as shown in FIG. 1A. Further, etching patterns masking material 30, as shown in FIG. 1B. As shown in FIG. 1C, masking material 30 is then used to etch first metal 10 over PMOS region 22. Masking material 30 has a high wet etch selectivity with respect to first metal 10 and gate dielectric layer 12. FIG. 1D shows first metal 10 remains over NMOS region 20, but is removed over PMOS region 22 selective to gate dielectric layer 12. As also shown in FIG. 1D, masking material 30 is removed. As shown in FIG. 1E, depositing a second, PMOS metal 40, a capping layer 42 and a polysilicon 44 are next. Conventionally, as shown in FIG. 1E, second metal 40 is deposited both on PMOS region 22 and NMOS region 20, and does not have to be removed over NMOS region 20 because first metal 10 is contacting gate dielectric layer 12 where the work function is primarily determined. Subsequent processing (not shown) patterns the gates from this material.
A number of challenges are presented by these processes. As shown in FIGS. 1C-1D, first metal 10 needs to be selectively removed from PMOS region 22 without damaging the underlying gate dielectric layer 12. Conventional photoresists, however, cannot be used for masking material 30 because first metal 10 etch chemistries, e.g., SPM, SC1, H2O2, etc., tend to etch masking material 30 with too high of an etch rate. In addition, when the photoresist masking material 30 is removed using wet etching, it is difficult to preserve first metal 10. Furthermore, as shown in FIG. 1D, gate dielectric layer 12 is continuously exposed to the wet chemical during masking material 30 removal, which may remove significant amounts of gate dielectric layer 12, especially if it contains silicon oxide. As photoresists cannot serve as masking material 30 during first metal 10 etch, other materials such as silicon oxide or silicon nitride have been used with some success. However, removing silicon oxide or silicon nitride based masking materials from gate dielectric layer 12, which may contain the same materials, without damaging layer 12 and first metal 10 is problematic. For example, hydrofluoric (HF) acid is typically used for etching a silicon oxide based mask because it has good selectivity with first metal 10. However, depending on gate dielectric layer 12 material, HF acid could significantly etch gate dielectric layer 12. Silicon nitride based masks have similar problems. It is possible to prevent over etching of gate dielectric layer 12 by using masking material 30 that has a high wet etch selectivity compared to the materials of gate dielectric layer 12 (e.g., silicon oxide or hafnium silicate). However, exposing gate dielectric layer 12 to wet chemicals also can cause various other problems, such as surface roughening, impurity absorption and gate work function modification. Accordingly, it is desirable not to expose gate dielectric layer 12 to the wet chemical during the integration.
The structure as illustrated in FIG. 1E also presents challenges relative to gate formation in subsequent steps (not shown). In particular, the heterogeneous metals (i.e., first metal layer 10 and second metal 40, on the single wafer poses a significant challenge for the gate stack dry etch stopping on gate dielectric layer 12. Since second metal 40 is different on NMOS region 20 and PMOS region 22, the dry etch chemistry has to be different. In order to remove both metals and stop on gate dielectric layer 12, sequential removal of the two metals has to be implemented in the dry etch recipe. This process is particularly difficult because gate dielectric layer 12 on one side of the wafer will be exposed to a dry etch ambient during etching of second metal 40. As a result, penetration of gate dielectric layer 12 is highly likely, leading to recessing of substrate 14. In order to avoid this situation, it is desirable to have the same metal contact gate dielectric layer 12 in both NMOS region 20 and PMOS region 22.
In view of the foregoing, there is a need in the art for a solution to the problems of the related art.